Novel electronic devices typically comprise several voltage domains with different supply voltage levels. These different voltage domains however need to communicate with each other. Some of the circuits may operate at a power supply level of 1.8 V or below. Accordingly, a circuit is required which can interface the two different voltage domains and which can tolerate a high voltage but which can also operate at lower supply voltages.
Typically, a native pass gate with its gate coupled to a supply voltage VDD limits the input voltage to the supply voltage VDD and passes an input signal to a receiver with input swings of up to VDD. For example, a native NMOS transistor comprises a significantly smaller threshold voltage (0-0.2 V) than a typical NMOS transistor (0.6 V). Due to body effects, the threshold voltage may even be larger, i.e. 0.4 V for a native transistor and 0.9 V for a typical transistor. In other words, a native device can pass voltages from VDD (VDD−VTH) to VSS. However, it should be noted that native devices are not available in all process technologies in the semiconductor industry. It should also be noted that a native device may add a significant additional cost to the cost of the device.
U.S. Pat. No. 6,768,339 B2 describes a 5 V tolerant input scheme with a switch CMOS pass gate. However, such an implementation is complex and requires a lot of area, and additional control signals are required which also introduce additional cost. Under certain conditions, a static current flow from VDD to VSS may be present, which may create a short between VDD and VSS and is thus not power efficient.
U.S. Pat. No. 6,771,113 B1 discloses a 5 V tolerant and fail-safe input circuit based on a source follower configuration to provide a high voltage tolerant circuit. However, because of the source follower and the resistor configuration, a constant static current is present in the circuit, i.e. the circuit is not power efficient.